Renesas Electronics /R7FA2A1AB /GPT320 /GTBER

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Interpret as GTBER

BD=0, CCRA=00, PR=00, CCRB=00, CCRSWT=0

Description

General PWM Timer Buffer Enable Register

Fields

BD	BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 (0): Buffer operation is enabled 1 (1): Buffer operation is disabled
CCRA	GTCCRA Buffer Operation 0 (00): Buffer operation is not performed 1 (01): Single buffer operation (GTCCRA <–> GTCCRC) 2 (10): Double buffer operation (GTCCRA <–> GTCCRC <–> GTCCRD) 3 (11): Double buffer operation (GTCCRA <–> GTCCRC <–> GTCCRD)
CCRB	GTCCRB Buffer Operation 0 (00): Buffer operation is not performed 1 (01): Single buffer operation (GTCCRB <–> GTCCRE) 2 (10): Double buffer operation (GTCCRB <–> GTCCRE <–> GTCCRF) 3 (11): Double buffer operation (GTCCRB <–> GTCCRE <–> GTCCRF)
PR	GTPR Buffer Operation 0 (others): Setting prohibited 0 (00): Buffer operation is not performed 1 (01): Single buffer operation (GTPBR --> GTPR)
CCRSWT	GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 0 (0): no effect 1 (1): Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1.

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